[Abaqus] Thermal Stress

[mohsen saadatmand [e-mail] [Abaqus]]

Hello everyone.
I'm working on the simulation of induced thermal stress due to coefficient of thermal expansion (CTE) difference between Cu layer and Si substrate.At first, the copper is deposited on the substrate (by PVD). Then copper diffuses into Trench (shown in attached file) by doing heat treatment. The aim of my work is to study the induced thermal stress during cooling step. Since the CTE of copper is greater than that of Si, as we expect, the copper layer placed out of trench should be under compression stress but inside of trench (due to constraints induced by sidewalls of Si) should be under tensile stress. I have some questions:
1- How can I define connection between Cu layer and substrate? 
2- I connected two materials using Tie constraint. In your mind, is it OK?
3- Results showed that the copper layer bends the Si substrate (after cooling). I think it is a little weird.
I defined thermal and elastic properties (temperature dependent) and static step. As boundary condition, I fixed the bottom of Si along all directions. I defined an initial temperature and final temperature at Predefined field.
Please kindly let me know if you can help me. 
Kind Regards,


Mohsen 




[Non-text portions of this message have been removed]

[Vahid Ebrahimzade [e-mail] [Abaqus]]

Hi


The inplane stress (tangential to the interface) should be for Cu tensile
because the substrate is preventing the Cu to shrink, and for Si the
opposite (at the room temperature I mean).


1- Tie constraint is Ok. You can also model you whole geometry and then
partition it and assign different materials to the two areas.
3- Based on what I said at first, I think Si is under compression at room
temperature. But are the stresses so high that it can bend the substrate??
I do not know. Usually the substrate have higher mechanical properties.


Hope it can help.

Post by mohsen saadatmand ***@yahoo.com [Abaqus]
Hello everyone.
I'm working on the simulation of induced thermal stress due to coefficient
of thermal expansion (CTE) difference between Cu layer and Si substrate.At
first, the copper is deposited on the substrate (by PVD). Then copper
diffuses into Trench (shown in attached file) by doing heat treatment. The
aim of my work is to study the induced thermal stress during cooling step.
Since the CTE of copper is greater than that of Si, as we expect, the
copper layer placed out of trench should be under compression stress but
inside of trench (due to constraints induced by sidewalls of Si) should be
1- How can I define connection between Cu layer and substrate?
2- I connected two materials using Tie constraint. In your mind, is it OK?
3- Results showed that the copper layer bends the Si substrate (after
cooling). I think it is a little weird.
I defined thermal and elastic properties (temperature dependent) and
static step. As boundary condition, I fixed the bottom of Si along all
directions. I defined an initial temperature and final temperature at
Predefined field.
Please kindly let me know if you can help me.
Kind Regards,
Mohsen
[Non-text portions of this message have been removed]